4-channel, 100 Gbps inductorless optical receiver analog front-end in CMOS for optical interconnect

In this paper, a 4-channel, 100 Gbps inductorless optical receiver analog front-end fabricated in 55 nm bulk-CMOS technology is presented. Active feedback technique widely adopted to improve the performance of without area-occupied inductors. To alleviate voltage headroom stress local loop traditional regulated cascode transimpedance amplifier, common gate amplifier inserted before source stage. And cross-couple active stage provides negative signal path extend bandwidth loop. Multi-stage limiting with and positive stages are employed acquire high gain simultaneously. The was realized as 4-element arrays occupying area $800\,\,\mu \text{m}\,\,\times 1800\,\,\mu \text{m}$ , whereas core each channel just $275\,\,\mu 650\,\,\mu . measured 3-dB reaches 22.8 GHz, sufficient for 25-Gbps operation. For an input 2.5 mV $_{\text {p-p}}$ achieves BER $= 10^{-12}$ at PRBS7, 310 differential output delivered. From supply 1.2 V, test chip consumes power 226 mW exhibits efficiency 2.3 mW/Gb/s, when PRBS31 supplied.